import chisel3._
import chisel3.util._

class BUFGCE extends BlackBox(Map("SIM_DEVICE" -> "7SERIES")) {
    val io = IO(new Bundle {
        val I = Input(Clock())
        val CE = Input(Bool())
        val O = Output(Clock())
    })
}

class Top_bufg extends Module {
    val io = IO(new Bundle {})
    val bufgce = Module(new BUFGCE)
    // 连接BUFGCE的时钟输入端口到顶层模块的时钟信号
    bufgce.io.I := clock
}

object Top_bufg extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(new Top_bufg())
    //ChiselStage.emitSystemVerilogFile(
    //new Top_bufg(),
    //firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
   //)
}

